Meeting Time to Volume Challenges

Prof. Sudhakar Reddy, over the course of his illustrious career has devoted his energies to solving VLSI testing problems. His research runs the gamut from Coding Theory, Self-Checkers and Fault Tolerance to Memory Testing, Design for Testability, ATPG and Test Pattern Compression. This forum seeks to celebrate Prof. Reddy’s contribution to the field of VLSI testing, and his efforts in fostering original thinking as a dedicated educator and mentor.

Today’s designs are larger, more sophisticated and integrate diverse features such as analog, digital, flash and DRAM in a monolithic substrate that were previously only possible on separate chips. Today’s process technology is more complex and the physics of devices and interconnects requires increasingly complex modeling. Yet, design cycles are shorter and leave little room for additional complexities. Thus, when the first silicon arrives, the task often is to validate the design assumptions and plug any gaps that impact yield and performance. "Getting things right the first time" in silicon platform validation is of critical importance as design iterations are costly and the window of market opportunity is small.

Testing plays a crucial role in validating a silicon platform. While rooted in the same principle, goals in silicon platform validation are vastly different from manufacturing test. Complexity of test pattern development against physical behaviors that account for parametric variations, throw up new challenges. Reduced manufacturing tolerance due to sub-wavelength lithography, time dependent device degradation along with interplay with environmental factors such as temperature and voltage require that we pay close attention to underlying physical behavior of the devices.

The forum will feature invited presentations and discussions in the topic areas including but not limited to:

Design for Testability
System-on-a-Chip (SOC) DFT
Memory and Logic BIST
Debug and Diagnosis Techniques
Test Scheduling and Test Resource Partitioning
Power and Noise-Aware Test
DFT for At-Speed Test
Self-Checking and Fault-Tolerant Techniques
Design for Manufacturing and Yield
Concurrent Error Detection
Testing for Iterative/ Reconfigurable Logic
Test Pattern Compression

Presentations

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The forum will provide opportunities for 2-3 minute personal presentations and 30 minute technical presentations. If you would like to contribute a presentation of either type please contact the program chair, Professor Kewal Saluja at saluja@ece.wisc.edu or (608) 262-6490.

For general information contact:

Sandip Kundu
University of Massachusetts, Amherst
Tel: +1-413-577-3309
Fax: +1-413-545-1993
E-mail: kundu@ecs.umass.edu

Committees

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General Chairs
S. Kundu, U. Mass.
Y. Zorian, Virage Logic

Program Chair
K.K. Saluja, U. Wisconsin

Vice Program Chair
I. Pomeranz, Purdue U

Industry Relations Chair
J. Rajski, Mentor

Local Arrangements Chair
S. Patil, Intel

Publicity Chair
D. S. Ha, Virginia Tech

European Liaisons
B. Becker, U. Freiburg
C. Landrault, LIRMM

Asian Liaisons
K. Kinoshita, Osaka-G U
C.W. Wu, NTHU

Program Committee
M. Abramovici - DAFCA
V. Agarwal - Logicvision
J. Ashjaee - Javad Navig
K. Fuchs - Cornell
H. Fujiwara - NAIST
S. Gupta - USC
A. Gunda - LSI Logic
N.K. Jha - Princeton
J.G. Kuhl - U Iowa
V. P. Kumar - Bell Labs
K.J. Lee - NCKU
M. Renovell - LIRMM
Nirmal Saxena
H. Tamamoto - Akita
S. Venkataraman – Intel

For more information, visit us on the web at: http://reddy.ecn.uiowa.edu

The TTTC Technical Forum in Honor of Prof. Sudhakar M. Reddy is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) Awards Program.

CALL FOR PRESENTATIONS
Overview -- Presentations -- Committees
Overview	top
Meeting Time to Volume Challenges Prof. Sudhakar Reddy, over the course of his illustrious career has devoted his energies to solving VLSI testing problems. His research runs the gamut from Coding Theory, Self-Checkers and Fault Tolerance to Memory Testing, Design for Testability, ATPG and Test Pattern Compression. This forum seeks to celebrate Prof. Reddy’s contribution to the field of VLSI testing, and his efforts in fostering original thinking as a dedicated educator and mentor. Today’s designs are larger, more sophisticated and integrate diverse features such as analog, digital, flash and DRAM in a monolithic substrate that were previously only possible on separate chips. Today’s process technology is more complex and the physics of devices and interconnects requires increasingly complex modeling. Yet, design cycles are shorter and leave little room for additional complexities. Thus, when the first silicon arrives, the task often is to validate the design assumptions and plug any gaps that impact yield and performance. "Getting things right the first time" in silicon platform validation is of critical importance as design iterations are costly and the window of market opportunity is small. Testing plays a crucial role in validating a silicon platform. While rooted in the same principle, goals in silicon platform validation are vastly different from manufacturing test. Complexity of test pattern development against physical behaviors that account for parametric variations, throw up new challenges. Reduced manufacturing tolerance due to sub-wavelength lithography, time dependent device degradation along with interplay with environmental factors such as temperature and voltage require that we pay close attention to underlying physical behavior of the devices. The forum will feature invited presentations and discussions in the topic areas including but not limited to: Design for Testability System-on-a-Chip (SOC) DFT Memory and Logic BIST Debug and Diagnosis Techniques Test Scheduling and Test Resource Partitioning Power and Noise-Aware Test DFT for At-Speed Test Self-Checking and Fault-Tolerant Techniques Design for Manufacturing and Yield Concurrent Error Detection Testing for Iterative/ Reconfigurable Logic Test Pattern Compression
Presentations	top
The forum will provide opportunities for 2-3 minute personal presentations and 30 minute technical presentations. If you would like to contribute a presentation of either type please contact the program chair, Professor Kewal Saluja at saluja@ece.wisc.edu or (608) 262-6490. For general information contact: Sandip Kundu University of Massachusetts, Amherst Tel: +1-413-577-3309 Fax: +1-413-545-1993 E-mail: kundu@ecs.umass.edu
Committees	top
General Chairs S. Kundu, U. Mass. Y. Zorian, Virage Logic Program Chair K.K. Saluja, U. Wisconsin Vice Program Chair I. Pomeranz, Purdue U Industry Relations Chair J. Rajski, Mentor Local Arrangements Chair S. Patil, Intel Publicity Chair D. S. Ha, Virginia Tech European Liaisons B. Becker, U. Freiburg C. Landrault, LIRMM Asian Liaisons K. Kinoshita, Osaka-G U C.W. Wu, NTHU Program Committee M. Abramovici - DAFCA V. Agarwal - Logicvision J. Ashjaee - Javad Navig K. Fuchs - Cornell H. Fujiwara - NAIST S. Gupta - USC A. Gunda - LSI Logic N.K. Jha - Princeton J.G. Kuhl - U Iowa V. P. Kumar - Bell Labs K.J. Lee - NCKU M. Renovell - LIRMM Nirmal Saxena H. Tamamoto - Akita S. Venkataraman – Intel
For more information, visit us on the web at: http://reddy.ecn.uiowa.edu
The TTTC Technical Forum in Honor of Prof. Sudhakar M. Reddy is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) Awards Program.